1. Field of the Invention
The present invention relates to computer systems, and more specifically to a computer system in which bus master control lines can be dynamically allocated to connected peripheral devices.
2. Description of Related Art
The PCI (Peripheral Component Interconnect) bus is a standardized local bus that is used for communication between a CPU and its peripherals. The PCI bus allows for system board connection of high-speed peripherals and for connecting add-in cards to the system board. The PCI bus now dominates the desktop PC (personal computer) market as the primary way of connecting peripherals to the CPU, and variants of the standard PCI bus have evolved for industrial, compact, and mobile applications. The PCI bus and connected devices operate in accordance with the PCI specification, which is published by the PCI Special Interest Group. Because it is processor independent, any CPU or peripheral can be connected to the bus. In accordance with revision 2.1 of the specification, the PCI bus can provide a 32 or 64 bit data path that operates at a 33 or 66 MHz clock rate.
In a conventional PC, a system board houses a central processing unit CPU and its associated main memory, which is typically a large block of DRAM. A cache of faster SRAM memory, a logic control chip set, a CPU bus, and a PCI bus are also provided on the system board. Peripherals (such as a network interface controller, a graphics controller, and a sound controller) are connected to the PCI bus in the form of add-in cards. An ISA bridge may also be provided to allow ISA bus-based peripherals to be connected to the computer system. Additionally, the system board usually has ports for input and output devices such as a keyboard, a mouse, and a printer.
The PCI bus provides bus request lines and bus grant lines that allow devices connected to the bus to operate as bus masters. For a peripheral device to act as a bus master, the device must have bus master capabilities (i.e., the ability to request access to the PCI bus and then to generate the signals that are necessary to complete the data transfer in accordance with the PCI specification). Additionally, a unique bus request/grant line pair must be provided for the device so that bus requests can be generated independent of other bus activity.
While a large number of devices could theoretically be operated as bus masters, conventional logic control chip sets offer only a limited number of PCI bus request/grant line pairs. For example, the widely used logic chip sets manufactured by Intel Corporation (Santa Clara, Calif.) provide only four PCI bus request/grant line pairs. Furthermore, in conventional systems, the bus request/grant line pairs are hard wired to specific system board devices or add-in card slots. If a bus request/grant line pair is wired to a special system board device such as a universal serial bus (USB) controller, the number of add-in card slots available for bus master devices is reduced.
For example, the single board computer design guidelines (from the PCI Industrial Computers Manufacturing Group) allow up to four PCI bus master devices to be connected as add-in cards. However, devices on the computer board itself may also need to operates as bus masters. In such a conventional computer system, even when the on-board device is not needed in the present system configuration (e.g., if no peripheral devices are connected to the USB), the number of other devices that can operate as bus masters is limited. In other words, regardless of which devices are actually installed and being used in the system, the only way to change the allocation of the bus request/grant line pairs is to change the system board.